`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:26:10 11/29/2011
// Design Name:   CPU_Pipelined
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/Cs3710/16bitcpu/Pipeline_simulation.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CPU_Pipelined
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Pipeline_simulation;

	// Inputs
	reg CLK;
	reg reset;
	reg [11:0] p1_input;
	reg [11:0] p2_input;

	// Outputs
	wire [9:0] ballx;
	wire [8:0] bally;
	wire [8:0] p1;
	wire [8:0] p2;
	wire [15:0] p1_score;
	wire [15:0] p2_score;

	// Instantiate the Unit Under Test (UUT)
	CPU_Pipelined uut (
		.CLK(CLK), 
		.reset(reset), 
		.ballx(ballx), 
		.bally(bally), 
		.p1(p1), 
		.p2(p2), 
		.p1_input(p1_input), 
		.p2_input(p2_input), 
		.p1_score(p1_score), 
		.p2_score(p2_score)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;
		p1_input = 0;
		p2_input = 0;

		// Wait 100 ns for global reset to finish

		#100;
		reset=1;
		#100;
		reset=0;
        
		// Add stimulus here

	end
	
	always begin
	#20 CLK=~CLK;
	end
      
      
endmodule

